Comments Locked

15 Comments

Back to Article

  • psychobriggsy - Tuesday, August 25, 2020 - link

    Can you imagine: 1 layer of CPU cores, 1 layer 'passive heatspreader silicon', 8 layers of SRAM, 1 layer of I/O and another passive layer.

    Or 4 layers of slower CPU/GPU cores and 8 layers of SRAM.

    64C Threadripper in a single stack with 512MB L3 cache...
  • Valantar - Tuesday, August 25, 2020 - link

    ... and a smoldering hole in your motherboard within seconds of powering on, I assume?

    On a more serious note, this sounds like it would have serious potential for shrinking SoCs in a dramatic way, but power and heat density would be an issue. It would also be interesting if TSMC were to cooperate with a memory manufacturer to get HBM into a setup like this. An 8-high stack of HBM + the active die at the base of the stack would leave three layers for something like a GPU. Or two stacks next to each other if you need more area for the GPU, of course. Could stick the less hot running parts like encode/decode on a layer below the main GPU layer.
  • name99 - Wednesday, August 26, 2020 - link

    Amazing.

    EVERY time 3D stacking is mentioned, we get the people telling us it won't work because of heat issues. Poor TSMC -- they spent billions developing this tech, but nobody in the company was smart enough to validate whether there were any use cases that won't be thermally overloaded.

    Oh well, that's what happens when you don't use random internet commenters to head your product strategy.
  • brunis.dk - Friday, August 28, 2020 - link

    Local warming is real! :D
  • saratoga4 - Sunday, August 30, 2020 - link

    Stacking for low power SOCs makes a lot of sense, but the OP's idea of a 64 core Zen processor under 8-12 layers is absolutely not going to happen for thermal reasons.
  • quadibloc - Tuesday, October 26, 2021 - link

    Well, it is obvious it won't work for the kinds of things that would be really exciting. But, yes, obviously it will work for stuff like DRAM.
  • astroboy888 - Thursday, August 27, 2020 - link

    A 2009 3DIC study done by Stanford comparing 3D stacked memory vs. traditional 2D connected memory founds that power dissipation can be reduced by as much as 5X in a 3D stacked configuration.

    https://isl.stanford.edu/people/abbas/papers/conf%...
  • Rudde - Wednesday, August 26, 2020 - link

    Having the cores on their own chiplets have its own advantages. It also keeps the power consumption down per stack. 512MB L3 cache for say 16 cores would be crazy amounts when scaled to 256 cores (16 chiplets) and beyond. The IO might also have its own stack allowing it to have larger/additional memory/pcie controllers.
    Why scale either out or up? Why not both?
  • MrEcho - Tuesday, August 25, 2020 - link

    It will be interesting to see how they deal with heat with so many layers. Maybe its only 2 layers of transistors, with all the interconnect logic between them. Transistor sandwich if you will :)
  • brucethemoose - Tuesday, August 25, 2020 - link

    Amazing! I can't even imagine the kind of precision they need to line everything up.

    I wonder how many layers they can eventually do? If they could stick enough system memory right below the compute dies, it would turn modern processor design on its head.
  • linuxgeex - Wednesday, August 26, 2020 - link

    Alignment is easy... they can let physics do it for them by patterning it in a way which produces static attraction which pulls them into fine alignment. Similar to how people can solder SMT and BGA chips in place without even being able to see the pads. Heat it up, you know it's in place when you see it jump, when nudging a corner causes it to move but spring immediately back. Static used to me a problem in micro-circuit assembly. Every problem presents an opportunity. :-)
  • rumaisa - Wednesday, August 26, 2020 - link

    Three-dimensional 3D mix utilizing through-silicon vias TSVs and low-volume without lead weld interconnects permits the arrangement of high sign transmission capacity, fine pitch, and short-separation interconnections in stacked kicks the bucket. There are a few methodologies for 3D chip stacking including https://www.gulfwriter.com/ chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip coordination and chip-to-wafer reconciliation offer the capacity to stack known great bites the dust, which can prompt more significant returns without incorporated repetition.
  • name99 - Wednesday, August 26, 2020 - link

    ???
    Is GPT3 now being used to write fake comments with embedded ads?
  • brucethemoose - Wednesday, August 26, 2020 - link

    Not yet. They just copy text from the article or other comments.

    Comment spam is bottom barrel, any high class spammer using a NN will focus their efforts elsewhere.
  • NiorLipstickinBd - Thursday, August 27, 2020 - link

    nice article.I also want to write a bong on it on my blogging page https://blog.carnesia.com/
    thanks for this idea

Log in

Don't have an account? Sign up now